- UnChol Song, JongSam Ri, NamChol Yu*
- DOI: 10.5281/zenodo.17186343
- GAS Journal of Engineering and Technology (GASJET)
A packet transmission network (PTN) is a transmission network based on packet switching technology, when using a packet transmission network for mobile backhaul (MBH), all nodes in the network must have frequency synchronization to achieve base-station synchronization through the network. Synchronous Ethernet (SyncE) is the most efficient frequency synchronization method available in a packet transmission network, where each node in the transmission network regenerates clock information at the physical layer level, filters jitter and offset through the phase-locked loop (PLL), and then delivers frequency by distributing it across the physical layer to the next nodes regardless of the higher layer transmission protocols. In this paper, in order to implement synchronous Ethernet-based frequency synchronization in packet transmission network, the synchronization block of 1G and 10G transmission equipment is composed of synchronous clock generation unit, jitter rejection and frequency multiplication unit, synchronous clock generation unit is implemented on FPGA (Field Programmable Gate Array) chip, jitter rejection and frequency multiplication unit is implemented on Si5328 chip, jitter attenuation precision clock synthesizer. Given that the PLL resource embedded in the FPGA chip is limited and does not satisfy the multiplication ratio required to obtain the synchronous clock from the receive regenerative clock outputted from the 10G physical layer device, the clock synchronized to the receive regenerative clock outputted by the physical layer is generated using only pure logic elements based on the Numerical Controller Oscillator (NCO) principle, so we have reduced PLL’s resource consumptions using this way. The jitter rejection and frequency multiplication unit eliminates the phase jitter from the synchronous clock to the receive regenerative clock detection unit and the synchronous clock generation unit, and sets the parameters of the Si5328 chip necessary to synthesize the transmitting clock of the physical layer device for synchronous Ethernet. In addition, the experimental system was constructed and measured with 1G and 10G transmitting nodes applying the proposed synchronization method. As a result, phase fluctuation was 23ns, which is consistent with the requirement of synchronous Ethernet specified in ITU-T Recommendation G.8262.